> -----Original Message----- > From: tclug-list-bounces at mn-linux.org > [mailto:tclug-list-bounces at mn-linux.org]On Behalf Of Jeremy > Sent: Tuesday, March 30, 2010 12:41 PM > To: TCLUG Mailing List > Subject: Re: [tclug-list] Languages My comments on a few you mentioned may not help the main thread, but may help clarify these citations: > matlab/scilab/octave - great for processing data through lots of formulae. Makes great approximate models, but is not great for representing real hardware that is processing measurable signals. Best used as abstract math that may approximate something real, but its results are never quite real or accurate... close or closer, but not accurate. > > VHDL, Verilog, JHDL, MyHDL, RHDL - SImilar to DHL or Fedex for bits of data, > For when it absolutely has to be there on time. About as low as you can go > with software. I disagree! These are metalanguages (VHDL AMS and Verilog AMS in particular... AMS = Analog and Mixed Signal). They can be as high in representation of system abstraction or in software expression, etc, as one can go, and certainly as "complete" as C or C++ or SPICE which are seamlessly connected to them and included if needed or useful for expressing lower-level stuff. VHDL and Verilog actually are capable of carrying from top block diagram or flow chart levels of system abstraction and behavior down seamlessly to nitty-gritty of device physics and processes, and exact design of the transistors that make your CPUs and memory and analog video, etc. These are far more versatile, precise, and expressive than MatLab, though not intended for the very same uses. MatLab is only a behavioral approximation for hardware or other reality, while Verilog AMS or VHDL AMS are full and complete and elegant means to describe, define, fabricate, and benchmark real hardware. This group of "languages" is seldom known or practiced in an IT group, but network stuff can be designed or analyzed with Verilog AMS or VHDL AMS stochastically or by discrete events, etc, to any degree of "quick and dirty" or detailed design. There is an open source version of VHDL AMS and possibilities of an open source Verilog AMS as well. Hardware jocks prefer Verilog's bottom up orientation, while VHDL has more software formality and data typing, etc. Chuck