On Thu, 17 May 2001, Matt Waters wrote:

>     When one of you guys put your SGI Indy up for sale, I told my friend
> about it, and we began arguing over the power of a risc processer. He argues 
> that because of a risc's limited instruction set, a risc is slower than a 
> comperable x86 because it requires more intructions to accomplish a task. I 
> argue that risc's have more bang per computational cycle, because the 
> instructions they use take up fewer clock cycles, and fewer instructions 
> means the cpu can transmit data more quickly.

Um, the thing that both of you are leaving out is that we're talking about
a programmable machine.  The reason it's a religious war starter, as *I*
understand it, is that it's really hard to compare apples to apples
anyway.  It depends largely on the task you want to do.  So, you might be
able to do the same thing equally efficiently, but the algorithm might
need to be completely different for the two machines.  Like a risc machine
might win using a bubble sort, but a cisc machine might win using an
insertion sort, and if you let each play to their strengths, they might
tie.  

Another example might be that x86 processors won't move memory to memory
without involving a register.  Maybe a MIPS (or other risc chip) does
allow this sometimes.  So for some things that just *move* data, the risc
processor kills, but slows down when you have to figure out how to make it
process.

The only thing I'd say about your statement is that saying that a risc
proc. has more bang per clock cycle is incorrect as phrased.  The
principle is that you puposely have *less* bang per cycle, but you "make
it up in volume."  

Doing a little looking at assembly code would be most instructive.  If you
write a little program in C, 'g++ -S ' will compile to a *.s file, which
is assembly code.  I think if you do the same and include the switch for
the MIPS target, you  will get some MIPS assy code.  You still don't know
how many cycles each instruction takes, but you'd get an idea of how
different the paths are to get to the same point.

> Plus, the 64-bit bus allows the cpu to handle data more efficiently.
> (My friend claims that PIIs and up use 128-bit buses with 32-bit
> compatibility mode.)

Wait, are you talking about the data/address bus, or are you talking about
the size of the registers?  Better define "efficient use of data" better
before you argue this one too far, I think.

-- 
"To misattribute a quote is unforgivable." --Anonymous